CNBeta — 2026-07-04#
Top Story#
According to a CNBeta report, Huawei’s HiSilicon head He Tingbo released the V2 paper detailing the evolution of Kirin and Ascend chips using “time scaling” (3D logic folding) instead of traditional geometric miniaturization. This marks a major pivot in semiconductor design strategy, showing how Chinese firms plan to bypass physical constraints and EDA bottlenecks through system-level continuous optimization, with Kirin 2026 demonstrating a 41% power reduction.